1. Technical Field
Various aspects of the present disclosure generally relate to a semiconductor apparatus, and more particularly, to a semiconductor memory apparatus that comprises a circuit and a method for controlling a faulty address in the semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus comprises memory cells which may fail to perform normal operations due to problems occurred in the manufacturing process and its operations. Since the size of a unit memory cell diminishes as the degree of integration in a memory apparatus increases, the number of memory cells which do not perform normal operations increases accordingly.
Based on the above, redundancy memory cells capable of replacing faulty memory cells are integrated to improve productivity. When an externally inputted address designates a faulty memory cell, a repair process is conducted such that the address of a redundancy memory cell replaces a logic address that accesses the corresponding faulty memory cell. Therefore, a semiconductor memory apparatus needs a circuit for storing the physical address of the faulty memory cell and a circuit that determines if an externally inputted address designates the faulty memory cell.
A method has been adopted to store the faulty address when a metal fuse corresponding to the faulty address is blown using a laser beam, which results in an open circuit.
FIG. 1 illustrates the faulty address storing method in accordance with a conventional art.
According to the art, a faulty address is recorded by cutting off relevant metal fuses to conduct a repair process. Specifically, as shown in FIG. 1, each of the metal fuses corresponding to the faulty address is heated by a laser beam. The heated fuses are then thermally expanded due to increase in the internal pressure, and blown, resulting in an open circuit.
FIGS. 2A and 2B show two diagrams that illustrate the operation of a conventional faulty address storage circuit.
FIG. 2A illustrates a faulty address storage circuit when the metal fuse F is not cut.
When the faulty address control signal EN is enabled, a node K1 is at a high level, and an output signal OUT is at the opposite phase of the input address ADD.
On the other hand, FIG. 2b illustrates a faulty address storage circuit where the fuse metal F is cut. In FIG. 2b, the node K1 is at a low level, and the output signal OUT has a phase that is the same as the input address ADD.
When a semiconductor memory apparatus uses an N-bit address system, values corresponding to the respective bits of the faulty address are stored in N-faulty address storage circuits, respectively. Each of them has the structure shown in FIGS. 2A and 2B. In other words, the metal fuses from the faulty address storage circuits corresponding to the high level bit values of an N-bit faulty address are cut. The respective bits of an externally inputted N-bit address are sequentially applied to the N-faulty address storage circuits to determine whether the externally inputted N-bit address matches the faulty address.
If some of the metal fuses are cut, the address storage circuits generate signals having the same level as the corresponding inputted address bits. If the metal fuses are not cut, signals with a level opposite to the inputted address are outputted. Then, a logical AND operation is performed on the output signals of the respective faulty address storage circuits. If a resultant output signal is high, it is decided that the corresponding redundancy cell should be accessed.
For example, if a faulty address is 0110, the metal fuses of faulty address storage circuits corresponding to the high bit values, or the second and third faulty address storage circuits, are cut.
Furthermore, if an externally inputted address is 0110 which is identical to the faulty address, all the respective output signals of four faulty address storage circuits become high. Therefore, since the resultant output signal obtained by performing an AND operation on the respective output signals is high, it is decided that an access to the redundancy cell is necessary.
Meanwhile, if the faulty address is 0110 and an externally inputted address is 0100, the four faulty address storage circuits output 1101 bits. Since the externally inputted address does not match the faulty address in this case, an access may be made to a memory cell which has a corresponding address of 0100.
However, since the repair scheme using metal fuses is based on the assumption that the laser beam never fails to reach the desired metal fuse, the metal fuse should be physically large enough to meet the assumption. This is one of the reasons to adversely affect the degree of integrity of semiconductor memory devices.
Furthermore, there is also a problem of increased cost due to expensive manufacturing equipments that should be used to store faulty addresses in the semiconductor memory devices, such as a laser irradiation device.